Abstract

   The SHA algorithm is one well-known and represents an important function in cryptographic systems used especially to assure data integrity and authenticity. Implementation on reprogrammable hardware structures is a solution that enables synthesis of algorithms in digital hardware modules that may operate at high speeds. In this work is being studied algorithm implementation of SHA-1, 24 bits on a Field Programmable Gate Array (FPGA) in order to obtain solutions to reduce the area of deployment. There are described constituent modules of the implementation and at the end of the paper are presented comparative results with other similar implementations.